1. Field of the Invention
The invention relates to a data transmission system in which computers or various control apparatus distributed in different locations are mutually connected by a common transmission medium for mutual data exchange, such as in a network of computers or automated machine controllers.
2. Description of the Related Art
Recent developments in factory automation have resulted in the construction of high-function, high-performance continuous process control systems. In such systems intelligent machines, such as computers, PCs (Programmable Controllers), and DCS (Distributed Control Systems), are connected to a common transmission medium to build a network. Such a networked system can exchange information, including production information (for example, manufacturing entry and product result), manufacturing program data and process control data. Moreover, such networked systems can monitor data among these multiple machines and execute decentralized control and supervisory control of the entire system. One type of continuous process control system shares supervisory data and control data which are to be exchanged among multiple machines, thus ensuring efficient decentralized control in individual machines and supervisory control of the entire system.
In a point-to-point type data transmission system employed for information exchange among individual machines, each machine transmits information to a specifically identified machine (the destination) and awaits acknowledgement of the reception of the information from that destination. The time consumed in complicated and troublesome handshaking and other duplicative procedures in multi-point and point-to-point communications has resulted in relatively slow response times in such point-to-point data transmission systems. As a result, broadcast and multicast data transmission systems have emerged. In one example of a broadcast or multicast data transmission, each machine hooked up to the data transmission system periodically transmits its data and other machines periodically receive these in-coming data, which they store internally for monitoring and controlling the application system. The monitor and control data typically is common to the entire system and is stored in a "common memory", CM, provided within each machine or node. The "common memory" in each node has the same configuration, at least for address and data purposes, to facilitate a common addressing scheme. The monitor/control data is stored in each common memory at a specific memory address common to the individual machines, thereby renewing the latest data periodically. U.S. Pat. No. 4,930,121 discloses a system having a plurality of common memories in a plurality of nodes with a common address structure. High-speed and effective information exchanges between a node and any number of destinations (multi-point type communication) are executed in this manner, to achieve decentralized control for each machine and supervisory control of the entire system. Examples of such a data transmission system are a data transmission system as disclosed in Published Examined Japanese Patent Application No. 64-8501 and a network system employing a token-passing bus system as disclosed in Published Unexamined Japanese Patent Application Nos. 1-157143, 3-45042.
FIG. 1 illustrates the construction of a local area network (LAN) system to be employed in a conventional continuous process control system. Multiple nodes 10.sub.1 to 10.sub.n are connected at proper distances to a common transmission medium L. Such nodes can correspond to the above described machines. Each of the nodes 10.sub.1 -10.sub.n has a common memory CM incorporated. Typically, the common memory in each node is substantially identical. The dashed line to each common memory CM, 27, in FIG. 1 indicates that each common memory stores the same information at the same address location. A node is authorized to use the transmission path to broadcast or multicast information within a predetermined time period. At the expiration of the predetermined time period that node gives the authorization to the next node. This is known as media access control. Although a ring network is constructed in FIG. 1, a bus network having individual nodes 10.sub.1 -10.sub.n connected in a bus form and a star network having the nodes connected in a star form are also possible configurations.
The IEEE (Institute of Electrical & Electronics Engineers) Standard 802.5 to be applied to a loop network, the FDDI system standardized by American National Standards Institute (ANSI), and the IEEE Standard 802.4 to be employed in the bus or star network can all be applied in this type of data transmission system. All of these systems are similar or applicable to media access control via a token. In a token-passing system individual nodes exchange a frame called "token" with one another. Possession of the token gives transmission authorization to a node, so that multiple nodes do not simultaneously have the permission to transmit at the same time. Since the node receiving the token must transmit data within a predetermined time period, the total number of nodes and the selected predetermined times for the individual nodes restrict the maximum time that a node must wait to transmit its data. The predetermined time periods may be the same or different for each node. The individual nodes send data in accordance with a predetermined order in which the token is passed to allow access to the transmission path.
In the LAN system shown in FIG. 1, each of the nodes 10.sub.1 to 10.sub.n broadcasts or multicasts a data frame to the other nodes. As shown in FIG. 2, the data frame includes the following fields: preamble (PA), start delimiter (SD), frame control (FC), destination address (DA), source address (SA), destination service access point (DSAP), source service access point (SSAP), information command (C), information word number (WN), address field (ADRS) output data (DATA.sub.0 -DATA.sub.n), and frame check sequence (FCS). An end delimiter (ED) may also be used.
When the other nodes all receive the data frame, the data frame is stored in the common memory CM at a specific address CM.sub.1. The node having authorization to use the transmission path gives the token to the next node when a predetermined time period has elapsed. The node receiving this token has the right to use the transmission path for a predetermined period of time, and likewise transmits its data frame. Thus, all the nodes 10.sub.1 -10.sub.n contain the same contents in each common memory, CM. FIG. 3 illustrates one example of a train of frames on the transmission path, which are transmitted by the individual nodes 10.sub.1, 10.sub.2 . . . , 10.sub.n in the order of the data frame D.sub.1, followed by the token TK, data frame D.sub.2 followed by the token TK, and so forth, within a predetermined transmission period T.
The nodes 10.sub.1 -10.sub.n each have the hardware configuration shown in FIG. 4. When one node having the authorization to use the transmission path, for example, the node 10.sub.1, transmits the data frame shown in FIG. 2, each of the other nodes 10.sub.2 -10.sub.n receives the data frame at transceiver circuit 20. Transceiver circuit 20 sends a received output 21 to receive and transmission control circuit 22. A receive and transmission control circuit 22 in each node checks the DA field in the received data frame to determine whether or not the received data is intended for that node. If an individual address designating only one node, a broadcast address or a multicast address in the DA field designates that node as an addressee, control circuit 22 determines that the received data is intended for that node and further processes the data frame. When control circuit 22 completes the reception of the data frame, a DMA (Direct Memory Access) control circuit 23 extracts the received data in the fields from the FC field to FCS field from the data frame and stores the data in a receive buffer 24.
The received data is stored in the receive buffer 24, as shown in FIG. 5A or 5B. FIG. 5A illustrates one example of a storage arrangement of receive buffer 24 in the case of proper or normal data reception without error, and FIG. 5B the storage status of receive buffer 24 when there is a reception error. In either case, in this example, the field length of the received data is "64" words. In these diagrams, STS (Status) is status information which indicates whether the reception has been properly completed or a reception error has occurred (determined for example, by a cyclic redundancy check), and LN (Length Number) represents the total quantity of data stored in the receive buffer 24.
Referring again to FIG. 4, a receive and transmission control processor 25 begins to process the received data upon reception of a data frame reception end signal sent along line 26 from the receive and transmission control circuit 22. The processing of the received data in receive and transmission control processor 25 is to determine if the DSAP field, the SSAP field and the C field in the received data stored in the receive buffer 24 match predefined values. If the required matches exist, the WN field, which indicates the total quantity of data in the received data field, and the ADRS (Address) field, which indicates the start memory address to store data in the common memory 27, are read out and the WN value and ADRS value are set in the DMA control circuit 23. The DMA control circuit 23 in turn transfers the received data.sub.0 to DATA.sub.n in the receive buffer 24 to the common memory 27. The data stored in the common memory 27 is read out via interface circuit 28 and utilized by host equipment 29, such as a computer, PC or DCS. After the received data is temporarily stored in receive buffer 24, the values in the WN field and ADRS field are read out and transferred to the associated address in the common memory 27.
FIG. 4 also shows buffer memory bus 40 a buffer memory data bus 41 and a buffer memory address bus 42, and a common memory bus 50 having a common memory data bus 51 and a common memory address bus 52. Host system bus 60 is also shown between interface circuit 28 and host equipment 29. A common memory bus control circuit (not shown) may also provided.
In the above described system, the receive buffer 24 and the common memory 27 are physically different from each other. Temporarily storing the data frame in the receive buffer 24 and transferring it for storage in common memory 27 results in long processing times. These processing times restrict the data transfer performance of the entire communication system. One reason for this is that host equipment 29 cannot access common memory 27 while the common memory and receive buffer 24 are exchanging data.
Even if the data transmission rate on the media could be increased to enhance performance, the processing time involved in transferring received data from the temporary storage in the receive buffer 24 to the final storage destination in common memory 27 is restricted by the data transfer performance of the common memory bus 50 between the receive buffer 24 and common memory 27. Thus, performance improvement is limited. Moreover, improving the data transmission rate to enhance the transfer performance requires complex hardware.
Related U.S. application Ser. No. 07/653,290, filed Feb. 11, 1990 attempts to eliminate the common memory by reading a start memory address from the receive buffer. An upper and lower address are then calculated and a carry acquired. The upper address is put together with a common memory address to access a lower address generating memory.